The present invention relates to Integrated Circuits (IC), and more particularly to controlling the timing of signals used in a memory embedded in an IC.
Advances in semiconductor fabrication processes which have enabled an ever increasing number of transistors to be formed on an IC fabricated on a single semiconductor substrate, have seen a parallel increase in the type and number of functions that such ICs may perform. One class of ICs enables its users to program functions that the IC is required to perform. This class comprises programmable ICs such as programmable logic devices (PLDs), field programmable gate arrays (FPGAs), microprocessors, coprocessors, microcontrollers, programmable controllers or sequencers, graphics controllers, memories, DRAMs, SRAMs, EPROMs, serial EPROMs, Flash memories, and many others.
The various hardware blocks, commonly known as logic array blocks, are typically not connected to one another when the FPGA is first supplied by its manufacturer. The user must first program the FPGA to carry out the functions specified by the user. Programming of an FPGA is usually performed with the aid of software in which the interconnections between various logic blocks are first specified. After being executed, the software causes the specified interconnections to occur, in other words, it programs the FPGA to create the desired logic and interconnections. An FPGA thus eliminates the need for design-intensive and time-consuming efforts required for custom-specific ICs.
An FPGA usually includes arrays of logic blocks that are programmable and are selectively connected to arrays of interconnect lines to attain both combinatorial as well as sequential logic functions. Programming of programmable logic blocks, as well as their connections to the selected lines (e.g., bus lines), is typically achieved by establishing the states of a multitude of programmable elements, such as configuration cells or fuses, disposed in the FPGA.
An FPGA typically includes, in addition to various other blocks, an array of static random access memory (SRAM) cells. The SRAM array may have a single port, used for both read and write operations, or a dual port with one port dedicated to read and another port dedicated to write operations, or with both ports implementing the read/write functions in parallel. FIG. 1 is a schematic diagram of a section of a single port read and write paths associated with SRAM cell 15. P-channel transistors 20, 22 and 24 precharge the true and complementary bitlines BL and BL to supply voltage Vcc prior to read and/or write operations. During a read operation, bitlines BL and BL are coupled to the sense amplifier 30 via transistors 32 and 34 and in response to read column select signal RCS. The sensed data are supplied as signals DOUT and DOUT. During a write operation, input data supplied using signals DIN and DIN are transferred to bitlines BL and BL via transistors 26 and 28 and in response to write column select signal WCS.
FIG. 2 is a timing diagram of the signals used during read and write operations, as shown in FIG. 1. In response to a low-to-high transition 50 on clock signal CLK following a read request (not shown), signal BLPC makes a high-to-low transition 52, signal WL makes a low-to-high transition 54, and signal RCS makes a high-to-low transition 56. Transition 52 of signal BLPC terminates the bitline precharge operation. Transition 54 of signal WL turns on transistors 42 and 44 to enable inverter pair 44 of SRAM cell 15 to be coupled to bitlines BL and BL thus enabling these bitlines to develop voltage differentials 58. At time T1, the voltage differentials on bitlines BL and BL, and corresponding dummy bitlines (not shown) reach a value that cause sense amp 30 to be enabled via transition 60 of signal SAE. Thereafter, sense amp 30, sensing the voltage differentials on bitlines BL and BL, generates output data signal DOUT. Following the completion of the read operation, the various signals described above are restored to their previous values.
In response to a low-to-high transition 80 on clock signal CLK following a write request (not shown), signal BLPC makes a high-to-low transition 82 thus terminating the bitline precharge operation. Transition 82 also causes signal WSC to make a low-to-high transition 84 to couple the bitlines BL and BL to the data input lines DIN and DIN in order to enable the new data to be stored in cell 15. Accordingly, after transition 84, bitlines BL and BL transition to their new complementary values, shown using transition 88, reflecting the new low value 86 of input data DIN. Thereafter, signal WL makes a low-to-high transition 90 to enable inverter pair 44 of cell 15 to be coupled to the bitlines carrying the new data, as represented by transition 92 on signal MC, representing the memory content. Following the completion of the write operation, the various signals described above are restored to their previous values, as seen in FIG. 2.
As is well known, successful completion of read and write operations in a dual-port SRAM embedded in an FPGA requires maintaining accurate timing margins between a number of critical signals. For example, to perform a successful read operation, bitline precharge signal BLPC must be turned off before the wordline select signal WL is asserted so as to allow a bitline voltage differential to develop before the sense amps are activated. Similarly, to perform a successful write operation, bitline precharge signal BLPC must be turned off before the write column select signal WCS is asserted to supply the new input data to the bit lines. Such timing margins during the various memory operations must be maintained for all qualified process, temperature and voltage variations.
As the technology for manufacturing FPGAs scales down into deep sub-micron, partly due to local random variations, the mathematical models used to account for actual variations in fabrication processes may become less accurate As a result, the timing margins and performance metrics may be subject to degradation. The timing margin degradations may also result in functional failure.